The present invention relates generally to the field of data processing systems, and more particularly to a data processor having a mathematically consistent condition code architecture for executing single instruction range checking and limiting operations.
With the advent of microprocessors, the number of applications using digital data processors has rapidly expanded. Due to their speed and versatility, microprocessors have been found to be particularly useful in performing control functions, as for example, in modern microprocessor based engine control systems. In such applications, it is often necessary to perform range checking and limiting operations on software variables to ensure that their values do not exceed acceptable limits.
In the past, these kind of range checking and limiting operations were typically accomplished by comparing the value of a software variable with a stored limiting value (upper or lower bound), and if the value of the variable exceeded the limiting value (greater than the upper bound or less than the lower bound), then the value of the variable was replaced by the limiting value. This process requires the execution of a sequence of several machine instructions for carrying out a single range checking and limiting operation. Since these operations are required frequently in programs employed in control applications, these sequences tend to consume large amounts of program memory and increase program execution time. Accordingly, there exists a need for a microprocessor that has the ability to perform a range checking and limiting operation on a software variable via a single machine instruction.
Another problem that is generally not addressed, when performing conventional range checking and limiting operations, is that of arithmetic overflow. An overflow occurs when a numeric result produced by an arithmetic operation (unsigned or signed) exceeds the permissible size of the data object's representation in the microprocessor's arithmetic logic unit (ALU), in which case the result is mathematically undefined. Consequently, to properly perform a range checking and limiting operation on a software variable, it first must be known whether the value of the variable is the result of an arithmetic overflow, and second, the direction of the overflow (either positive or negative) must also be known. If such information is not available when performing range checking and limiting operations, the software variable may not be limited when it actually should have been, or it may be set to the wrong limiting value (i.e., set to the upper limiting value when it should have been set to the lower limiting value, or vice versa).
In conventional microprocessor systems, arithmetic overflow conditions resulting from the execution of mathematical operations in the ALU are typically indicated by setting condition code bits (flags) in a status register. Existing condition code architectures usually provide an indication of unsigned arithmetic overflow by setting a condition code carry bit (C-bit). This bit is set whenever an arithmetic operation generates a carry-out or a borrow-in within the ALU, which produces unsigned arithmetic overflow in the positive or negative direction, respectively. However, the carry bit is generally not used exclusively as an unsigned overflow indicator. It is also used as a bit accumulator during ALU shift and rotate operations. Shift operations are commonly used as optimized multiply and divide (by powers of two) operations, and when so used, the C-bit is not always a valid unsigned overflow indicator (depending upon the type of shift operation performed). Also, some data processors include unsigned multiply and divide operations in their instruction sets, which generally do not treat the C-bit as an unsigned overflow indicator.
Indications of signed arithmetic overflow are typically provided by a condition code overflow bit (V-bit). This bit is usually set when an arithmetic operation generates a result that cannot be properly represented in 2's complement form in the ALU. Since 2's complement numbers can be positive or negative, signed arithmetic overflow also occurs in either a positive or negative direction. Historically, for simple operations such as add, subtract, and compare, the states of the V-bit, and a condition code negative bit (N-bit) have been used to indicate both a signed overflow and its direction. For example, when the V-bit and the N-bit are both set to logic 1 values, signed overflow is said to be in the positive direction, and when V-bit is set to a logic 1 value and the N-bit is set to a logic 0 value, signed overflow is said to be in the negative direction. Here again, traditional condition code architectures do not provide for setting the condition codes to correctly indicate signed overflow with direction for shift, multiply and divide operations. Thus, existing condition code architectures do not behave in a systematic fashion when indicating the occurrence of overflow for the various arithmetic operations.
In order to correctly perform range limiting and checking operations, a condition code architecture that deals consistently with arithmetic overflows produced by arithmetic operations is required. Since it is not always possible or practical to ascertain the exact arithmetic instruction used in performing a particular arithmetic operation (for example, a shift may be used for multiplying or dividing by powers of two), all of the instructions in a microprocessor's instruction set that can be used to perform arithmetic operations must provide the necessary arithmetic overflow and direction of arithmetic overflow information in a consistent manner. This applies to instructions for performing primitive arithmetic operations (such as add, subtract, and arithmetic shift operations, including logical shifts), as well as to those instructions performing operations that can be decomposed into sequences of primitive arithmetic operations (such as multiply and divide operations).
In the description that follows the term "mathematically consistent" will be used when referring to condition codes and condition code architectures that deal with the occurrence of arithmetic overflow (unsigned and/or signed) in a consistent manner, when executing all instructions in a microprocessor's instruction set that are capable of performing arithmetic operations. Unless a microprocessor includes such a condition code architecture, the exceptions and special cases required for dealing with the various arithmetic instructions would make range checking and limiting sequences complex, lengthy, and nearly impossible to implement in a single instruction format.
In view of the foregoing, there exists a need for a data processing system that includes a mathematically consistent condition code architecture for executing single instruction range checking and limiting operations.